Test MP+dmb.sy+[fr-rf]-addr-ctrl-data-rfi

AArch64 MP+dmb.sy+[fr-rf]-addr-ctrl-data-rfi
"DMB.SYdWW Rfe FrLeave RfBack DpAddrdR DpCtrldR DpDatadW Rfi Fre"
Cycle=Rfi Fre DMB.SYdWW Rfe FrLeave RfBack DpAddrdR DpCtrldR DpDatadW
Relax=
Safe=Rfi Rfe Fre DMB.SYdWW DpAddrdR DpDatadW DpCtrldR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe FrLeave RfBack DpAddrdR DpCtrldR DpDatadW Rfi Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X5=z; 1:X7=a; 1:X9=x;
2:X1=y;
}
 P0          | P1                  | P2          ;
 MOV W0,#2   | LDR W0,[X1]         | MOV W0,#2   ;
 STR W0,[X1] | LDR W2,[X1]         | STR W0,[X1] ;
 DMB SY      | EOR W3,W2,W2        |             ;
 MOV W2,#1   | LDR W4,[X5,W3,SXTW] |             ;
 STR W2,[X3] | CBNZ W4,LC00        |             ;
             | LC00:               |             ;
             | LDR W6,[X7]         |             ;
             | EOR W8,W6,W6        |             ;
             | ADD W8,W8,#1        |             ;
             | STR W8,[X9]         |             ;
             | LDR W10,[X9]        |             ;
Observed
    y=1; x=2; 1:X2=0; 1:X10=1; 1:X0=2;
and y=2; x=1; 1:X2=0; 1:X10=1; 1:X0=2;
and y=1; x=1; 1:X2=0; 1:X10=1; 1:X0=2;
and y=2; x=1; 1:X2=0; 1:X10=1; 1:X0=1;
and y=1; x=1; 1:X2=0; 1:X10=1; 1:X0=1;